@INPROCEEDINGS{SRAM_1,
  author={Kasai, G. and Takarabe, Y. and Furumi, K. and Yoneda, M.},
  booktitle={Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.}, 
  title={200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme}, 
  year={2003},
  volume={},
  number={},
  pages={387-390},
  keywords={Computer aided manufacturing;CADCAM;Circuits;Capacitance;Voltage;Energy consumption;Random access memory;Logic;Internet;Packet switching},
  doi={10.1109/CICC.2003.1249424}}
@ARTICLE{SRAM_2,
  author={Sungdae Choi and Sohn, K. and Hoi-Jun Yoo},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture}, 
  year={2005},
  volume={40},
  number={1},
  pages={254-260},
  keywords={Computer aided manufacturing;CADCAM;Repeaters;Voltage;Transistors;Timing;Testing;CMOS process;Energy efficiency;Content-addressable memory (CAM);hidden bank selection (HBS);high speed;hybrid type;low power;match line repeater (MLRPT)},
  doi={10.1109/JSSC.2004.837979}}
@ARTICLE{SRAM_3,
  author={Perng-Fei Lin and Kuo, J.B.},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell}, 
  year={2001},
  volume={36},
  number={4},
  pages={666-675},
  keywords={Cache memory;Computer aided manufacturing;CADCAM;Very large scale integration;CMOS technology;Pulse generation;Signal generators;Energy consumption;Low voltage;Paper technology},
  doi={10.1109/4.913745}}
@ARTICLE{SRAM_4,
  author={Hayashi, Isamu and Amano, Teruhiko and Watanabe, Naoya and Yano, Yuji and Kuroda, Yasuto and Shirata, Masaya and Dosaka, Katsumi and Nii, Koji and Noda, Hideyuki and Kawai, Hiroyuki},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS}, 
  year={2013},
  volume={48},
  number={11},
  pages={2671-2680},
  keywords={Sensors;Power demand;Noise;Computer architecture;Timing;Transistors;Discharges (electric);Differential sense amplifier;low-voltage matchline;reference voltage generator;ternary content-addressable memory (TCAM);voltage down converter},
  doi={10.1109/JSSC.2013.2274888}}
@INPROCEEDINGS{SRAM_5,
  author={Jeloka, Supreet and Akesh, Naveen and Sylvester, Dennis and Blaauw, David},
  booktitle={2015 Symposium on VLSI Circuits (VLSI Circuits)}, 
  title={A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell}, 
  year={2015},
  volume={},
  number={},
  pages={C272-C273},
  keywords={Computer aided manufacturing;Arrays;Decoding;SRAM cells;Transistors;Discharges (electric)},
  doi={10.1109/VLSIC.2015.7231285}}
@INPROCEEDINGS{SRAM_6,
  author={Do, Anh Tuan and Yin, Chun and Yeo, Kiat Seng and Kim, Tony Tae-Hyoung},
  booktitle={2013 Proceedings of the ESSCIRC (ESSCIRC)}, 
  title={Design of a power-efficient CAM using automated background checking scheme for small match line swing}, 
  year={2013},
  volume={},
  number={},
  pages={209-212},
  keywords={Computer aided manufacturing;Sensors;Delays;Power demand;Random access memory;Generators;Associative memory;CAM;small match line swing;match-line;variation tolerant design},
  doi={10.1109/ESSCIRC.2013.6649109}}
@ARTICLE{SRAM_7,
author={Wang, Chua-Chin and Hsu, Chia-Hao and Huang, Chi-Chun and Wu, Jun-Han},
journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
title={A Self-Disabled Sensing Technique for Content-Addressable Memories},
year={2010},
volume={57},
number={1},
pages={31-35},
keywords={Computer aided manufacturing;CADCAM;Energy consumption;Multilevel systems;Circuits;Costs;Power dissipation;Voltage;Switches;Differential amplifiers;Content-addressable memories (CAMs);match line sense amplifier (MLSA);nand-type CAM cell;self-disabled},
doi={10.1109/TCSII.2009.2037995}}
@ARTICLE{SRAM_8,
author={Yang, Byung-Do and Lee, Yong-Kyu and Sung, Si-Woo and Min, Jae-Joong and Oh, Jae-Mun and Kang, Hyeong-Ju},
journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
title={A Low Power Content Addressable Memory Using Low Swing Search Lines},
year={2011},
volume={58},
number={12},
pages={2849-2858},
keywords={Power demand;Computer architecture;MOSFETs;Associative memory;Content addressable memory (CAM);low swing;match line;nand cell;nor cell;search line},
doi={10.1109/TCSI.2011.2158703}}
@INPROCEEDINGS{SRAM_9,
  author={Sultan, M. and Siddiqui, M. and Sonika and Visweswaran, G .S},
  booktitle={TENCON 2008 - 2008 IEEE Region 10 Conference}, 
  title={A low-power ternary content addressable memory (TCAM) with segmented and non-segmented matchlines}, 
  year={2008},
  volume={},
  number={},
  pages={1-5},
  keywords={Associative memory;Multilevel systems;Logic;Capacitance;Cams;Paper technology;Energy consumption;CMOS technology;Computer aided manufacturing;CADCAM},
  doi={10.1109/TENCON.2008.4766746}}
@ARTICLE{SRAM_10,
  author={Chen, Jian and Zhao, Wenfeng and Wang, Yuqi and Shu, Yuhao and Jiang, Weixiong and Ha, Yajun},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, 
  title={A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations}, 
  year={2022},
  volume={30},
  number={6},
  pages={769-780},
  keywords={Reliability;Transistors;Random access memory;Sensors;Integrated circuit reliability;Voltage;Standards;Content addressable memory (CAM);in-memory computing (IMC);read disturbance;SRAM},
  doi={10.1109/TVLSI.2022.3164756}}
@ARTICLE{SRAM_11,
  author={Arsovski, I. and Chandler, T. and Sheikholeslami, A.},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme}, 
  year={2003},
  volume={38},
  number={1},
  pages={155-158},
  keywords={Voltage;Computer aided manufacturing;CADCAM;MOS devices;Circuit simulation;Energy consumption;Multilevel systems;Random access memory;Clocks;Pattern matching},
  doi={10.1109/JSSC.2002.806264}}
@INPROCEEDINGS{SRAM_12,
  author={Roth, A. and Foss, D. and McKenzie, R. and Perry, D.},
  booktitle={Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)}, 
  title={Advanced ternary CAM circuits on 0.13 /spl mu/m logic process technology}, 
  year={2004},
  volume={},
  number={},
  pages={465-468},
  keywords={Computer aided manufacturing;CADCAM;Multivalued logic;Logic circuits;Random access memory;Energy consumption;Capacitance;Impedance matching;Circuit synthesis;Variable structure systems},
  doi={10.1109/CICC.2004.1358852}}
@INPROCEEDINGS{SRAM_13,
  author={Wang, Chao-Ching and Cheng, Chieh-Jen and Chen, Tien-Fu and Wang, Jinn-Shyan},
  booktitle={2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers}, 
  title={An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices}, 
  year={2008},
  volume={},
  number={},
  pages={390-622},
  keywords={Computer aided manufacturing;CADCAM;Random access memory;Circuits;Engines;Pattern matching;Filtering;Merging;Energy consumption;Hardware},
  doi={10.1109/ISSCC.2008.4523221}}
@ARTICLE{SRAM_14,
  author={Wang, Chao-Ching and Wang, Jinn-Shyan and Yeh, Chingwei},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={High-Speed and Low-Power Design Techniques for TCAM Macros}, 
  year={2008},
  volume={43},
  number={2},
  pages={530-540},
  keywords={Circuits;Energy consumption;Associative memory;Clocks;Search engines;Buffer storage;Pipeline processing;Throughput;Chaos;Routing;Associative memories;content-addressable memory;high speed;low power;PF-CDPD;pseudo-footless;segmented search line;tree match line},
  doi={10.1109/JSSC.2007.914330}}
@ARTICLE{SRAM_15,
  author={Lin, Zhiting and Zhu, Zhiyong and Zhan, Honglan and Peng, Chunyu and Wu, Xiulong and Yao, Yuan and Niu, Jianchao and Chen, Junning},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports}, 
  year={2021},
  volume={56},
  number={9},
  pages={2832-2844},
  keywords={Random access memory;Transistors;SRAM cells;Logic gates;Writing;Microprocessors;Circuit stability;Binary content-addressable memory (CAM) (BCAM);in-memory computing;logic operation;SRAM;ternary CAM (TCAM);von Neumann bottleneck},
  doi={10.1109/JSSC.2021.3061260}}
@INPROCEEDINGS{SRAM_15,
  author={Arsovski, Igor and Wistort, Reid},
  booktitle={IEEE Custom Integrated Circuits Conference 2006}, 
  title={Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories}, 
  year={2006},
  volume={},
  number={},
  pages={453-456},
  keywords={Computer aided manufacturing;CADCAM;Timing;Uncertainty;Automatic testing;Time measurement;Power measurement;Energy consumption;Hardware;Robustness},
  doi={10.1109/CICC.2006.320819}}
INPROCEEDINGS{SRAM_17,
  author={Arsovski, I. and Nadkarni, R.},
  booktitle={Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.}, 
  title={Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines}, 
  year={2005},
  volume={},
  number={},
  pages={447-450},
  keywords={Computer aided manufacturing;CADCAM;Voltage;Power supplies;Laser sintering;Multilevel systems;Noise reduction;Switches;Working environment noise;Circuit noise},
  doi={10.1109/CICC.2005.1568702}}
@ARTICLE{SRAM_18,
  author={Huang, Po-Tsang and Hwang, Wei},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A 65 nm 0.165 fJ/Bit/Search 256 $\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables}, 
  year={2011},
  volume={46},
  number={2},
  pages={507-519},
  keywords={Power demand;Delay;Logic gates;Computer aided manufacturing;Clocks;Leakage current;Switches;Butterfly match-line;hierarchy search-line;memory;power gating;TCAM;XOR conditional keeper},
  doi={10.1109/JSSC.2010.2082270}}
article{SRAM_19,
author = {Yang, Shun-Hsun and Huang, Yu-Jen and Li, Jin-Fu},
title = {A low-power ternary content addressable memory with Pai-Sigma matchlines},
year = {2012},
issue_date = {October 2012},
publisher = {IEEE Educational Activities Department},
address = {USA},
volume = {20},
number = {10},
issn = {1063-8210},
url = {https://doi.org/10.1109/TVLSI.2011.2163205},
doi = {10.1109/TVLSI.2011.2163205},
abstract = {This paper proposes a Pai-Sigma matchline scheme to reduce the compare (search) power of a ternary content addressable memory (TCAM). The proposed matchline does not incur the issues of charge sharing and short circuit current, which typically exist in the hybrid NAND-NOR matchline. Moreover, the switching activity of the search lines of a TCAM with the proposed matchlines is low. A 32\texttimes{}64-bit TCAM with the Pai-Sigma matchlines is implemented to demonstrate the low-power feature. Results show that the compare power of the TCAM can achieve 60\% energy reduction compared with the conventional NOR-type TCAM. Also, the energy consumption per bit per search of the TCAM is only 2.287 fJ/bit/search.},
journal = {IEEE Trans. Very Large Scale Integr. Syst.},
month = {oct},
pages = {1909–1913},
numpages = {5},
keywords = {content addressable memories (CAM), low power, networking, ternary CAM (TCAM)}
}
@ARTICLE{DRAM_20,
  author={Noda, H. and Inoue, K. and Kuroiwa, M. and Igaue, F. and Yamamoto, K. and Mattausch, H.J. and Koide, T. and Amo, A. and Hachisuka, A. and Soeda, S. and Hayashi, I. and Morishita, F. and Dosaka, K. and Arimoto, K. and Fujishima, K. and Anami, K. and Yoshihara, T.},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture}, 
  year={2005},
  volume={40},
  number={1},
  pages={245-253},
  keywords={Power dissipation;Random access memory;Large-scale systems;Redundancy;Computer aided manufacturing;CADCAM;Integrated circuit yield;Costs;Silicon;Yield estimation;CMOS memory integrated circuits;embedded DRAM;network;ternary CAM},
  doi={10.1109/JSSC.2004.838016}}
@INPROCEEDINGS{DRAM_21,
  author={Noda, H. and Inoue, K. and Mattausch, H.J. and Koide, T. and Arimoto, K.},
  booktitle={2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)}, 
  title={A cost-efficient dynamic Ternary CAM in 130 nm CMOS technology with planar complementary capacitors and TSR architecture}, 
  year={2003},
  volume={},
  number={},
  pages={83-84},
  keywords={CMOS technology;Computer aided manufacturing;CADCAM;Capacitors;Random access memory;Writing;Clocks;Scheduling;Read-write memory;Capacitance},
  doi={10.1109/VLSIC.2003.1221168}}
@ARTICLE{DRAM_22,
author={Gupta, Navneet and Makosiej, Adam and Shrimali, Hitesh and Amara, Amara and Vladimirescu, Andrei and Anghel, Costin},
journal={IEEE Transactions on Nanotechnology}, 
title={Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM}, 
year={2021},
volume={20},
number={},
pages={270-277},
keywords={TFETs;Random access memory;Capacitors;Logic gates;Throughput;Capacitance;Doping;Tunnel FET;DRAM;eDRAM;metal-insulator-metal (MIM) capacitors;SRAM;CAM;CPU;GPU},
doi={10.1109/TNANO.2021.3061607}}
@INPROCEEDINGS{ReRAM_1,
  author={Chang, Meng-Fan and Lin, Chien-Chen and Lee, Albert and Kuo, Chia-Chen and Yang, Geng-Hau and Tsai, Hsiang-Jen and Chen, Tien-Fu and Sheu, Shyh-Shyuan and Tseng, Pei-Ling and Lee, Heng-Yuan and Ku, Tzu-Kun},
  booktitle={2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers}, 
  title={17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time}, 
  year={2015},
  volume={},
  number={},
  pages={1-3},
  keywords={Nonvolatile memory;Program processors;Very large scale integration;Computer architecture;Delays;CMOS process;MOSFET},
  doi={10.1109/ISSCC.2015.7063054}}
@INPROCEEDINGS{ReRAM_2,
  author={Li, Jing and Montoye, Robert and Ishii, Masatoshi and Stawiasz, Kevin and Nishida, Takeshi and Maloney, Kim and Ditlow, Gary and Lewis, Scott and Maffitt, Tom and Jordan, Richard and Chang, Leland and Song, Peilin},
  booktitle={2013 Symposium on VLSI Technology}, 
  title={1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing}, 
  year={2013},
  volume={},
  number={},
  pages={C104-C105},
  keywords={Encoding;Phase change materials;Sensors;Arrays;Microprocessors;Clocks},
  doi={}}
@INPROCEEDINGS{ReRAM_3,
  author={Lin, Chien-Chen and Hung, Jui-Yu and Lin, Wen-Zhang and Lo, Chieh-Pu and Chiang, Yen-Ning and Tsai, Hsiang-Jen and Yang, Geng-Hau and King, Ya-Chin and Lin, Chrong Jung and Chen, Tien-Fu and Chang, Meng-Fan},
  booktitle={2016 IEEE International Solid-State Circuits Conference (ISSCC)}, 
  title={7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell}, 
  year={2016},
  volume={},
  number={},
  pages={136-137},
  keywords={Nonvolatile memory;Sensors;Threshold voltage;Logic gates;Very large scale integration;Search engines;Resistance},
  doi={10.1109/ISSCC.2016.7417944}}
@inproceedings{ReRAM_4,
author = {Huang, Li-Yue and Chang, Meng-Fan and Chuang, Ching-Hao and Kuo, Chia-Chen and Chen, Chien-Fu and Yang, Geng-Hau and Tsai, Hsiang-Jen and Chen, Tien-Fu and Sheu, Shyh-Shyuan and Su, Keng-Li and Chen, Frederick and Ku, Tzu Kun and Tsai, Ming-Jinn and Kao, Ming-Jer},
year = {2014},
month = {06},
pages = {1-2},
title = {ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing},
isbn = {978-1-4799-3328-0},
doi = {10.1109/VLSIC.2014.6858404}
}
@Article{ReRAM_5,
author={Li, Can
and Graves, Catherine E.
and Sheng, Xia
and Miller, Darrin
and Foltin, Martin
and Pedretti, Giacomo
and Strachan, John Paul},
title={Analog content-addressable memories with memristors},
journal={Nature Communications},
year={2020},
month={Apr},
day={02},
volume={11},
number={1},
pages={1638},
abstract={A content-addressable memory compares an input search word against all rows of stored words in an array in a highly parallel manner. While supplying a very powerful functionality for many applications in pattern matching and search, it suffers from large area, cost and power consumption, limiting its use. Past improvements have been realized by using memristors to replace the static random-access memory cell in conventional designs, but employ similar schemes based only on binary or ternary states for storage and search. We propose a new analog content-addressable memory concept and circuit to overcome these limitations by utilizing the analog conductance tunability of memristors. Our analog content-addressable memory stores data within the programmable conductance and can take as input either analog or digital search values. Experimental demonstrations, scaled simulations and analysis show that our analog content-addressable memory can reduce area and power consumption, which enables the acceleration of existing applications, but also new computing application areas.},
issn={2041-1723},
doi={10.1038/s41467-020-15254-4},
url={https://doi.org/10.1038/s41467-020-15254-4}
}
@ARTICLE{ReRAM_6,
  author={Chang, Meng-Fan and Lin, Chien-Chen and Lee, Albert and Chiang, Yen-Ning and Kuo, Chia-Chen and Yang, Geng-Hau and Tsai, Hsiang-Jen and Chen, Tien-Fu and Sheu, Shyh-Shyuan},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing}, 
  year={2017},
  volume={52},
  number={6},
  pages={1664-1679},
  keywords={Nonvolatile memory;Transistors;Power demand;Resistive RAM;Delays;Logic gates;Servers;Nonvolatile memory (NVM);nonvolatile ternary content-addressable-memory (nvTCAM);resistive RAM (ReRAM);TCAM},
  doi={10.1109/JSSC.2017.2681458}}
@article{ReRAM_7,
author = {Khan, Masoodur and Rashid, ABM Harun-ur},
year = {2021},
month = {03},
pages = {},
title = {Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell},
volume = {15},
journal = {IET Circuits, Devices & Systems},
doi = {10.1049/cds2.12057}
}
@ARTICLE{MTJ_1,
  author={Song, Byungkyu and Na, Taehui and Kim, Jung Pill and Kang, Seung H. and Jung, Seong-Ook},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs}, 
  title={A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area}, 
  year={2017},
  volume={64},
  number={6},
  pages={700-704},
  keywords={Computer architecture;Microprocessors;Transistors;Nonvolatile memory;Integrated circuit reliability;Sensors;Cross-coupled PMOSs;differential MTJ sensing;magnetic tunnel junction (MTJ);nonvolatile TCAM (NV-TCAM);search operation;ternary content addressable memory (TCAM)},
  doi={10.1109/TCSII.2016.2594827}}
@article{MTJ_2,
  title={A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture},
  author={Shoun Matsunaga and Sadahiko Miura and Hiroaki Honjo and Keizo Kinoshita and Shoji Ikeda and Tetsuo Endoh and Hideo Ohno and Takahiro Hanyu},
  journal={2012 Symposium on VLSI Circuits (VLSIC)},
  year={2012},
  pages={44-45},
  url={https://api.semanticscholar.org/CorpusID:3449145}
}


@article{MTJ_3,
author = {Matsunaga, Shoun and Natsui, Masanori and Ikeda, Shoji and Miura, Katsuya and Endoh, Tetsuo and Ohno, Hideo and Hanyu, Takahiro},
year = {2011},
month = {06},
pages = {063004},
title = {Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme},
volume = {50},
journal = {Japanese Journal of Applied Physics},
doi = {10.7567/JJAP.50.063004}
}
@ARTICLE{MTJ_4,
       author = {{Matsunaga}, Shoun and {Katsumata}, Akira and {Natsui}, Masanori and {Endoh}, Tetsuo and {Ohno}, Hideo and {Hanyu}, Takahiro},
        title = {Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory},
      journal = {Japanese Journal of Applied Physics},
         year = 2012,
        month = feb,
       volume = {51},
       number = {2S},
          eid = {02BM06},
        pages = {02BM06},
          doi = {10.1143/JJAP.51.02BM06},
       adsurl = {https://ui.adsabs.harvard.edu/abs/2012JaJAP..51bBM06M},
      adsnote = {Provided by the SAO/NASA Astrophysics Data System}
}

@ARTICLE{MTJ_5,
  author={Xu, Wei and Zhang, Tong and Chen, Yiran},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, 
  title={Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed}, 
  year={2010},
  volume={18},
  number={1},
  pages={66-74},
  keywords={Magnetoresistance;Computer aided manufacturing;CADCAM;Read-write memory;Nonvolatile memory;Magnetic tunneling;CMOS technology;Scalability;Random access memory;Associative memory;Content addressable memory (CAM);magnetic tunneling junction (MTJ);magnetoresistive random access memory (MRAM);spin-torque transfer (STT) magnetoresistive memory;ternary CAM (TCAM)},
  doi={10.1109/TVLSI.2008.2007735}}
@INPROCEEDINGS{MTJ_6,
  author={Matsunaga, Shoun and Katsumata, Akira and Natsui, Masanori and Fukami, Shunsuke and Endoh, Tetsuo and Ohno, Hideo and Hanyu, Takahiro},
  booktitle={2011 Symposium on VLSI Circuits - Digest of Technical Papers}, 
  title={Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control}, 
  year={2011},
  volume={},
  number={},
  pages={298-299},
  keywords={Voltage measurement;Discharges;Magnetic tunneling;Semiconductor device measurement;Arrays;Voltage control;Nonvolatile memory},
  doi={}}
@INPROCEEDINGS{MTJ_7,
  author={Linuo Xue and Yuanqing Cheng and Jianlei Yang and Peiyuan Wang and Yuan Xie},
  booktitle={2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, 
  title={ODESY: A novel 3T-3MTJ cell design with optimized area density, scalability and latency}, 
  year={2016},
  volume={},
  number={},
  pages={1-8},
  keywords={Sensors;Microprocessors;Computer architecture;Magnetic tunneling;Resistance;Reliability;Scalability},
  doi={10.1145/2966986.2967060}}


@ARTICLE{FeFET_1,
  author={Yin, Xunzhao and Ni, Kai and Reis, Dayane and Datta, Suman and Niemier, Michael and Hu, Xiaobo Sharon},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs}, 
  title={An Ultra-Dense 2FeFET TCAM Design Based on a Multi-Domain FeFET Model}, 
  year={2019},
  volume={66},
  number={9},
  pages={1577-1581},
  keywords={Semiconductor device modeling;Logic gates;Iron;Delays;Hysteresis;Transistors;Resistance;Nonvolatile memory;content addressable storage;ferroelectric device},
  doi={10.1109/TCSII.2018.2889225}}
@INPROCEEDINGS{FeFET_2,
  author={Yin, Xunzhao and Niemier, Michael and Hu, X. Sharon},
  booktitle={Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017}, 
  title={Design and benchmarking of ferroelectric FET based TCAM}, 
  year={2017},
  volume={},
  number={},
  pages={1444-1449},
  keywords={Computer architecture;Magnetic tunneling;Microprocessors;Iron;MOSFET;Layout},
  doi={10.23919/DATE.2017.7927219}}
@article{FeFET_3,
  title={FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric},
  author={Xunzhao Yin and Chao Li and Qingrong Huang and Li Zhang and Michael Thaddeus Niemier and Xiaobo Sharon Hu and Cheng Zhuo and Kai Ni},
  journal={IEEE Transactions on Electron Devices},
  year={2020},
  volume={67},
  pages={2785-2792},
  url={https://api.semanticscholar.org/CorpusID:214802295}
}
@article{FeFET_4,
  title={Ferroelectric ternary content-addressable memory for one-shot learning},
  author={Kai Ni and Xunzhao Yin and Ann Franchesca Laguna and Siddharth Joshi and Stefan Dunkel and Martin Trentzsch and Johannes Muller and Sven Beyer and Michael Thaddeus Niemier and Xiaobo Sharon Hu and Suman Datta},
  journal={Nature Electronics},
  year={2019},
  volume={2},
  pages={521 - 529},
  url={https://api.semanticscholar.org/CorpusID:257095008}
}
ARTICLE{CapCAM_1,
  author={Ma, Xiaoyang and Zhong, Hongtao and Xiu, Nuo and Chen, Yiming and Yin, Guodong and Narayanan, Vijaykrishnan and Liu, Yongpan and Ni, Kai and Yang, Huazhong and Li, Xueqing},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, 
  title={CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications}, 
  year={2022},
  volume={30},
  number={11},
  pages={1770-1782},
  keywords={FeFETs;Voltage;Iron;Random access memory;Logic gates;Arrays;Sensors;Content-addressable memory (CAM);ferroelectric field-effect transistor (FeFET);low-power design;multiple-level CAM;pattern matching},
  doi={10.1109/TVLSI.2022.3198492}}
misc{ReRAM_8,
title={An Energy-efficient Capacitive-Memristive Content Addressable Memory}, 
author={Yihan Pan and Adrian Wheeldon and Mohammed Mughal and Shady Agwa and Themis Prodromakis and Alexantrou Serb},
year={2024},
eprint={2401.09207},
archivePrefix={arXiv},
primaryClass={eess.SY}
}


ARTICLE{other_reram,
  author={Yang, Yuanfan and Mathew, Jimson and Chakraborty, Rajat Subhra and Ottavi, Marco and Pradhan, Dhiraj K.},
  journal={IEEE Transactions on Nanotechnology}, 
  title={Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications}, 
  year={2016},
  volume={15},
  number={3},
  pages={527-538},
  keywords={Memristors;Computer aided manufacturing;Resistance;Transistors;Microprocessors;Computer architecture;CMOS integrated circuits;Content-addressable Memory (CAM);CMOL;low-power design;memristors;Content-addressable memory;CMOS molecular (CMOL);low-power design;memristors},
  doi={10.1109/TNANO.2016.2553438}}


@misc{other_analog_designs,
      title={Efficient Analog CAM Design}, 
      author={Jinane Bazzi and Jana Sweidan and Mohammed E. Fouda and Rouwaida Kanj and Ahmed M. Eltawil},
      year={2022},
      eprint={2203.02500},
      archivePrefix={arXiv},
      primaryClass={cs.AR}
}




@inproceedings{app_gen_1,
author = {Jahshan, Zuher and Merlin, Itay and Garz\'{o}n, Esteban and Yavits, Leonid},
title = {DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification},
year = {2023},
isbn = {9798400703294},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3613424.3614262},
doi = {10.1145/3613424.3614262},
abstract = {We propose a novel dynamic storage-based approximate search content addressable memory (DASH-CAM) for computational genomics applications, particularly for identification and classification of viral pathogens of epidemic significance. DASH-CAM provides 5.5 \texttimes{} better density compared to state-of-the-art SRAM-based approximate search CAM. This allows using DASH-CAM as a portable classifier that can be applied to pathogen surveillance in low-quality field settings during pandemics, as well as to pathogen diagnostics at points of care. DASH-CAM approximate search capabilities allow a high level of flexibility when dealing with a variety of industrial sequencers with different error profiles. DASH-CAM achieves up to 30\% and 20\% higher F1 score when classifying DNA reads with 10\% error rate, compared to state-of-the-art DNA classification tools MetaCache-GPU and Kraken2 respectively. Simulated at 1GHz, DASH-CAM provides 1, 178 \texttimes{} and 1, 040 \texttimes{} average speedup over MetaCache-GPU and Kraken2 respectively.},
booktitle = {Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture},
pages = {1453–1465},
numpages = {13},
keywords = {Approximate search, Content Addressable Memory, Dynamic approximate search, GC-eDRAM, Pathogen classification, Pathogen detection},
location = {<conf-loc>, <city>Toronto</city>, <state>ON</state>, <country>Canada</country>, </conf-loc>},
series = {MICRO '23}
}
@ARTICLE{app_gen_2,
  author={Garzón, Esteban and Golman, Roman and Jahshan, Zuher and Hanhan, Robert and Vinshtok-Melnik, Natan and Lanuzza, Marco and Teman, Adam and Yavits, Leonid},
  journal={IEEE Access}, 
  title={Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification}, 
  year={2022},
  volume={10},
  number={},
  pages={28080-28093},
  keywords={Hamming distance;DNA;Discharges (electric);Transistors;Pattern matching;Genomics;Bioinformatics;Approximate search;content addressable memory;DNA classification;hamming distance (HD)},
  doi={10.1109/ACCESS.2022.3158305}}
@INPROCEEDINGS{app_gen_3,
  author={Chen, Fan and Song, Linghao and Li, Hai “Helen” and Chen, Yiran},
  booktitle={2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)}, 
  title={PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM}, 
  year={2020},
  volume={},
  number={},
  pages={175-180},
  keywords={Genomics;DNA;Throughput;Computational efficiency;Arrays;Bioinformatics;Software tools},
  doi={10.1109/ASP-DAC47756.2020.9045555}}
@misc{app_gen_4,
      title={ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory}, 
      author={Hongtao Zhong and Zhonghao Chen and Wenqin Huangfu and Chen Wang and Yixin Xu and Tianyi Wang and Yao Yu and Yongpan Liu and Vijaykrishnan Narayanan and Huazhong Yang and Xueqing Li},
      year={2023},
      eprint={2302.07478},
      archivePrefix={arXiv},
      primaryClass={cs.AR}
}
@ARTICLE{app_gen_5,
  author={Yavits, L.},
  journal={IEEE Computer Architecture Letters}, 
  title={DRAMA: Commodity DRAM Based Content Addressable Memory}, 
  year={2024},
  volume={23},
  number={1},
  pages={65-68},
  keywords={Random access memory;Humanities;DNA;Voltage;Timing;Three-dimensional displays;Hardware;CAM;DRAM},
  doi={10.1109/LCA.2023.3341830}}
@inproceedings{app_gen_6,
author = {Kaplan, Roman and Yavits, Leonid and Ginosasr, Ran},
title = {BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data},
year = {2020},
isbn = {9781450375887},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3383669.3398279},
doi = {10.1145/3383669.3398279},
abstract = {Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming algorithm, such as Smith-Waterman. Traditional von Neumann architectures have limited parallelism and cannot provide an efficient solution for large-scale genomic data. Approximate heuristic methods (e.g. BLAST) are commonly used. However, they are suboptimal and still compute-intensive.In this work, we present BioSEAL, a biological sequence alignment accelerator. BioSEAL is a massively parallel non-von Neumann processing-in-memory architecture for large-scale DNA and protein sequence alignment. BioSEAL is based on resistive content addressable memory, capable of energy-efficient and highperformance associative processing.We present an associative processing algorithm for entire database sequence alignment on BioSEAL and compare its performance and power consumption with state-of-art solutions. We show that BioSEAL can achieve up to 57\texttimes{} speedup and 156\texttimes{} better energy efficiency, compared with existing solutions for genome sequence alignment and protein sequence database search.},
booktitle = {Proceedings of the 13th ACM International Systems and Storage Conference},
pages = {36–48},
numpages = {13},
location = {Haifa, Israel},
series = {SYSTOR '20}
}
@article{app_gen_7, title={A CAM (Content Addressable Memory) Architecture for Codon Matching in DNA Sequences}, volume={10}, url={https://journalcjast.com/index.php/CJAST/article/view/197}, DOI={10.9734/BJAST/2015/19154}, abstractNote={&amp;lt;p&amp;gt;DNA sequences are long strands of four letters – A,T.C and G,&amp;amp;nbsp; that represent the amino-acid building components of proteins . A triplet sequence of adjacent letters on a DNA sequence is known as a codon. Multiple codons represent one of the 20 possible amino acids. DNA sequence matching is used to determine the similarity between an unidentified DNA sequence with the database of other sequences with known characteristics. Those sequences displaying high levels of similarity tend to be similar in nature and thus the matching can be a useful tool in determining the nature of the new genetic sample. This paper presents the conceptual architecture of a content addressable memory that can be used to provide simultaneous comparison of a query DNA sequence with 16 stored sequences, and identifies the ones with the highest number of codon matches with the query sequence.&amp;lt;/p&amp;gt;}, number={5}, journal={Current Journal of Applied Science and Technology}, author={Lala, Parag K.}, year={2015}, month={Jul.}, pages={1–8} }
@ARTICLE{app_gen_8,
  author={Merlin, Itay and Garzón, Esteban and Fish, Alex and Yavits, Leonid},
  journal={IEEE Transactions on Computers}, 
  title={DIPER: Detection and Identification of Pathogens using Edit distance-tolerant Resistive CAM}, 
  year={2023},
  volume={},
  number={},
  pages={1-12},
  keywords={DNA;Pathogens;Genomics;Bioinformatics;Sequential analysis;Pandemics;Hamming distances;DNA detection and classification;content addressable memory;approximate search;resistive memory;memristors},
  doi={10.1109/TC.2023.3315829}}




@INPROCEEDINGS{app_hamdist_1,
  author={Li, Taixin and Zhong, Hongtao and George, Sumitha and Narayanan, Vijaykrishnan and Shi, Liang and Yang, Huazhong and Li, Xueqing},
  booktitle={2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, 
  title={Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays}, 
  year={2023},
  volume={},
  number={},
  pages={1-6},
  keywords={Associative memory;Nanoelectromechanical systems;Nonvolatile memory;Random access memory;Very large scale integration;Transistors;Hamming distances;multi-level ternary content addressable memory;nanoelectromechanical relay;dynamic memory},
  doi={10.1109/ISVLSI59464.2023.10238633}}


@misc{app_AI_1,
      title={Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration}, 
      author={Hanqing Zhu and Keren Zhu and Jiaqi Gu and Harrison Jin and Ray Chen and Jean Anne Incorvia and David Z. Pan},
      year={2022},
      eprint={2208.08099},
      archivePrefix={arXiv},
      primaryClass={cs.ET}
}
@INPROCEEDINGS{app_AI_2,
  author={Song, Tao and Chen, Xiaoming and Zhang, Xiaoyu and Han, Yinhe},
  booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)}, 
  title={BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System}, 
  year={2021},
  volume={},
  number={},
  pages={1033-1038},
  keywords={Design automation;Convolution;Simulation;Digital-analog conversion;Pipelines;Neural networks;Energy efficiency},
  doi={10.1109/DAC18074.2021.9586247}}
@Article{app_AI_3,
author={Pedretti, Giacomo
and Graves, Catherine E.
and Serebryakov, Sergey
and Mao, Ruibin
and Sheng, Xia
and Foltin, Martin
and Li, Can
and Strachan, John Paul},
title={Tree-based machine learning performed in-memory with memristive analog CAM},
journal={Nature Communications},
year={2021},
month={Oct},
day={04},
volume={12},
number={1},
pages={5806},
abstract={Tree-based machine learning techniques, such as Decision Trees and Random Forests, are top performers in several domains as they do well with limited training datasets and offer improved interpretability compared to Deep Neural Networks (DNN). However, these models are difficult to optimize for fast inference at scale without accuracy loss in von Neumann architectures due to non-uniform memory access patterns. Recently, we proposed a novel analog content addressable memory (CAM) based on emerging memristor devices for fast look-up table operations. Here, we propose for the first time to use the analog CAM as an in-memory computational primitive to accelerate tree-based model inference. We demonstrate an efficient mapping algorithm leveraging the new analog CAM capabilities such that each root to leaf path of a Decision Tree is programmed into a row. This new in-memory compute concept for enables few-cycle model inference, dramatically increasing 103{\thinspace}{\texttimes}{\thinspace}the throughput over conventional approaches.},
issn={2041-1723},
doi={10.1038/s41467-021-25873-0},
url={https://doi.org/10.1038/s41467-021-25873-0}
}
@misc{app_AI_4,
      title={RACE-IT: A Reconfigurable Analog CAM-Crossbar Engine for In-Memory Transformer Acceleration}, 
      author={Lei Zhao and Luca Buonanno and Ron M. Roth and Sergey Serebryakov and Archit Gajjar and John Moon and Jim Ignowski and Giacomo Pedretti},
      year={2023},
      eprint={2312.06532},
      archivePrefix={arXiv},
      primaryClass={cs.AR}
}
@INPROCEEDINGS{app_AI_5,
  author={Laguna, Ann Franchesca and Kazemi, Arman and Niemier, Michael and Hu, X. Sharon},
  booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, 
  title={In-Memory Computing based Accelerator for Transformer Networks for Long Sequences}, 
  year={2021},
  volume={},
  number={},
  pages={1839-1844},
  keywords={Energy consumption;Associative memory;Recurrent neural networks;Graphics processing units;Bandwidth;Parallel processing;Hardware;Transformers;crossbars;TCAM;LSH;parallelization;in-Memory Computing},
  doi={10.23919/DATE51398.2021.9474146}}
@ARTICLE{app_AI_6,
  
AUTHOR={Laguna, Ann Franchesca and Sharifi, Mohammed Mehdi and Kazemi, Arman and Yin, Xunzhao and Niemier, Michael and Hu, X. Sharon},   
         
TITLE={Hardware-Software Co-Design of an In-Memory Transformer Network Accelerator},      
        
JOURNAL={Frontiers in Electronics},      
        
VOLUME={3},           
        
YEAR={2022},      
          
URL={https://www.frontiersin.org/articles/10.3389/felec.2022.847069},       
        
DOI={10.3389/felec.2022.847069},      
        
ISSN={2673-5857},   
   
ABSTRACT={Transformer networks have outperformed recurrent and convolutional neural networks in terms of accuracy in various sequential tasks. However, memory and compute bottlenecks prevent transformer networks from scaling to long sequences due to their high execution time and energy consumption. Different neural attention mechanisms have been proposed to lower computational load but still suffer from the memory bandwidth bottleneck. In-memory processing can help alleviate memory bottlenecks by reducing the transfer overhead between the memory and compute units, thus allowing transformer networks to scale to longer sequences. We propose an in-memory transformer network accelerator (iMTransformer) that uses a combination of crossbars and content-addressable memories to accelerate transformer networks. We accelerate transformer networks by (1) computing in-memory, thus minimizing the memory transfer overhead, (2) caching reusable parameters to reduce the number of operations, and (3) exploiting the available parallelism in the attention mechanism computation. To reduce energy consumption, the following techniques are introduced: (1) a configurable attention selector is used to choose different sparse attention patterns, (2) a content-addressable memory aided locality sensitive hashing helps to filter the number of sequence elements by their importance, and (3) FeFET-based crossbars are used to store projection weights while CMOS-based crossbars are used as an attentional cache to store attention scores for later reuse. Using a CMOS-FeFET hybrid iMTransformer introduced a significant energy improvement compared to the CMOS-only iMTransformer. The CMOS-FeFET hybrid iMTransformer achieved an 8.96× delay improvement and 12.57× energy improvement for the Vanilla transformers compared to the GPU baseline at a sequence length of 512. Implementing BERT using CMOS-FeFET hybrid iMTransformer achieves 13.71× delay improvement and 8.95× delay improvement compared to the GPU baseline at sequence length of 512. The hybrid iMTransformer also achieves a throughput of 2.23 K samples/sec and 124.8 samples/s/W using the MLPerf benchmark using BERT-large and SQuAD 1.1 dataset, an 11× speedup and 7.92× energy improvement compared to the GPU baseline.}
}


@inproceedings{app_hashing_1,
author = {Bremler-barr, Anat and Harchol, Yotam and Hay, David and Hel-Or, Yacov},
year = {2015},
month = {05},
pages = {1-10},
title = {Ultra-Fast Similarity Search Using Ternary Content Addressable Memory},
doi = {10.1145/2771937.2771938}
}

@ARTICLE{app_hashing_3,
  author={Kazemi, Arman and Sharifi, Mohammad Mehdi and Laguna, Ann Franchesca and Müller, Franz and Yin, Xunzhao and Kämpfe, Thomas and Niemier, Michael and Hu, X. Sharon},
  journal={IEEE Transactions on Computers}, 
  title={FeFET Multi-Bit Content-Addressable Memories for In-Memory Nearest Neighbor Search}, 
  year={2022},
  volume={71},
  number={10},
  pages={2565-2576},
  keywords={FeFETs;Cams;Programming;Threshold voltage;Iron;Hardware;Switches;Associative memories;design styles;memory structures;hardware;memory used as logic;logic design;emerging technologies;general;computer systems organization},
  doi={10.1109/TC.2021.3136576}}
@ARTICLE{app_hashing_4,
  author={Liu, Liu and Laguna, Ann Franchesca and Rajaei, Ramin and Sharifi, Mohammad Mehdi and Kazemi, Arman and Yin, Xunzhao and Niemier, Michael and Hu, Xiaobo Sharon},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, 
  title={A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance}, 
  year={2023},
  volume={70},
  number={6},
  pages={2356-2369},
  keywords={Cams;FeFETs;Computer architecture;Microprocessors;DNA;Filtering;Encoding;Content addressable memory (CAM);threshold match;FeFET;reconfiguration;DNA read mapping;protein alignment;k-mismatch problem},
  doi={10.1109/TCSI.2023.3259940}}
@article{FeFET_4,
  title={Ferroelectric ternary content-addressable memory for one-shot learning},
  author={Kai Ni and Xunzhao Yin and Ann Franchesca Laguna and Siddharth Joshi and Stefan Dunkel and Martin Trentzsch and Johannes Muller and Sven Beyer and Michael Thaddeus Niemier and Xiaobo Sharon Hu and Suman Datta},
  journal={Nature Electronics},
  year={2019},
  volume={2},
  pages={521 - 529},
  url={https://api.semanticscholar.org/CorpusID:257095008}
}
@ARTICLE{app_hashing_6,
  author={Lee, Jae Seong and Yoon, Jisoo and Choi, Woo Young},
  journal={IEEE Electron Device Letters}, 
  title={In-Memory Nearest Neighbor Search With Nanoelectromechanical Ternary Content-Addressable Memory}, 
  year={2022},
  volume={43},
  number={1},
  pages={154-157},
  keywords={Nanoelectromechanical systems;Artificial neural networks;Nearest neighbor methods;Integrated circuit modeling;Resistance;Nanoscale devices;Transistors;Ternary content-addressable memory (TCAM);nearest neighbor search;memory-augmented neural network (MANN);nanoelectromechanical (NEM) memory switch;CMOS-NEM hybrid circuit},
  doi={10.1109/LED.2021.3131184}}
@Article{app_hashing_7,
author={Mao, Ruibin
and Wen, Bo
and Kazemi, Arman
and Zhao, Yahui
and Laguna, Ann Franchesca
and Lin, Rui
and Wong, Ngai
and Niemier, Michael
and Hu, X. Sharon
and Sheng, Xia
and Graves, Catherine E.
and Strachan, John Paul
and Li, Can},
title={Experimentally validated memristive memory augmented neural network with efficient hashing and similarity search},
journal={Nature Communications},
year={2022},
month={Oct},
day={21},
volume={13},
number={1},
pages={6284},
abstract={Lifelong on-device learning is a key challenge for machine intelligence, and this requires learning from few, often single, samples. Memory-augmented neural networks have been proposed to achieve the goal, but the memory module must be stored in off-chip memory, heavily limiting the practical use. In this work, we experimentally validated that all different structures in the memory-augmented neural network can be implemented in a fully integrated memristive crossbar platform with an accuracy that closely matches digital hardware. The successful demonstration is supported by implementing new functions in crossbars, including the crossbar-based content-addressable memory and locality sensitive hashing exploiting the intrinsic stochasticity of memristor devices. Simulations show that such an implementation can be efficiently scaled up for one-shot learning on more complex tasks. The successful demonstration paves the way for practical on-device lifelong learning and opens possibilities for novel attention-based algorithms that were not possible in conventional hardware.},
issn={2041-1723},
doi={10.1038/s41467-022-33629-7},
url={https://doi.org/10.1038/s41467-022-33629-7}
}



@inproceedings{ultra_fast_CAM,
author = {Bremler-barr, Anat and Harchol, Yotam and Hay, David and Hel-Or, Yacov},
year = {2015},
month = {05},
pages = {1-10},
title = {Ultra-Fast Similarity Search Using Ternary Content Addressable Memory},
doi = {10.1145/2771937.2771938}
}

@article{types_dcam,
author = {Pedretti, Giacomo and Graves, Catherine E. and Van Vaerenbergh, Thomas and Serebryakov, Sergey and Foltin, Martin and Sheng, Xia and Mao, Ruibin and Li, Can and Strachan, John Paul},
title = {Differentiable Content Addressable Memory with Memristors},
journal = {Advanced Electronic Materials},
volume = {8},
number = {8},
pages = {2101198},
keywords = {analog computing, content addressable memories, in-memory computing, memristor},
doi = {https://doi.org/10.1002/aelm.202101198},
url = {https://onlinelibrary.wiley.com/doi/abs/10.1002/aelm.202101198},
eprint = {https://onlinelibrary.wiley.com/doi/pdf/10.1002/aelm.202101198},
abstract = {Abstract Memristors, Flash, and related nonvolatile analog device technologies offer in-memory computing structures operating in the analog domain, such as accelerating linear matrix operations in array structures. These take advantage of analog tunability and large dynamic range. At the other side, content addressable memories (CAM) are fast digital lookup tables which effectively perform nonlinear Boolean logic and return a digital match/mismatch value. Recently, nonvolatile analog CAMs have been presented merging analog storage and analog search operations with digital match/mismatch output. However, CAM blocks cannot easily be inserted within a larger adaptive system due to the challenges of training and learning with binary outputs. Here, a missing link between analog crossbar arrays and CAMs, namely a differentiable content addressable memory (dCAM), is presented. Utilizing nonvolatile memories that act as a “soft” memory with analog outputs, dCAM enables learning and fine-tuning of the memory operation and performance. Four applications are quantitatively evaluated to highlight the capabilities: improved data pattern storage, improved robustness to noise and variability, reduced energy and latency performance, and an application to solving Boolean satisfiability optimization problems. The use of dCAM is envisioned as a core building block of fully differentiable computing systems employing multiple types of analog compute operations and memories.},
year = {2022}
}

@ARTICLE{types_optical_1,
  author={Kazemi, Arman and Sharifi, Mohammad Mehdi and Laguna, Ann Franchesca and Müller, Franz and Yin, Xunzhao and Kämpfe, Thomas and Niemier, Michael and Hu, X. Sharon},
  journal={IEEE Transactions on Computers}, 
  title={FeFET Multi-Bit Content-Addressable Memories for In-Memory Nearest Neighbor Search}, 
  year={2022},
  volume={71},
  number={10},
  pages={2565-2576},
  keywords={FeFETs;Cams;Programming;Threshold voltage;Iron;Hardware;Switches;Associative memories;design styles;memory structures;hardware;memory used as logic;logic design;emerging technologies;general;computer systems organization},
  doi={10.1109/TC.2021.3136576}}
@ARTICLE{types_optical_2,
  author={Liu, Liu and Laguna, Ann Franchesca and Rajaei, Ramin and Sharifi, Mohammad Mehdi and Kazemi, Arman and Yin, Xunzhao and Niemier, Michael and Hu, Xiaobo Sharon},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, 
  title={A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance}, 
  year={2023},
  volume={70},
  number={6},
  pages={2356-2369},
  keywords={Cams;FeFETs;Computer architecture;Microprocessors;DNA;Filtering;Encoding;Content addressable memory (CAM);threshold match;FeFET;reconfiguration;DNA read mapping;protein alignment;k-mismatch problem},
  doi={10.1109/TCSI.2023.3259940}}

@ARTICLE{types_optical_3,
  author={Mourgias-Alexandris, G. and Vagionas, C. and Tsakyridis, A. and Maniotis, P. and Pleros, N.},
  journal={IEEE Photonics Technology Letters}, 
  title={Optical Content Addressable Memory Matchline for 2-bit Address Look-Up at 10 Gb/s}, 
  year={2018},
  volume={30},
  number={9},
  pages={809-812},
  keywords={Adaptive optics;Optical sensors;Semiconductor optical amplifiers;Optical switches;Stimulated emission;Optical packet switching;Optical memories;content addressable memories;semiconductor optical amplifiers;optical look-up;photonic integrated circuits;InP monolithic integration},
  doi={10.1109/LPT.2018.2817928}}

@ARTICLE{types_optical_4,
  author={Lee, Jae Seong and Yoon, Jisoo and Choi, Woo Young},
  journal={IEEE Electron Device Letters}, 
  title={In-Memory Nearest Neighbor Search With Nanoelectromechanical Ternary Content-Addressable Memory}, 
  year={2022},
  volume={43},
  number={1},
  pages={154-157},
  keywords={Nanoelectromechanical systems;Artificial neural networks;Nearest neighbor methods;Integrated circuit modeling;Resistance;Nanoscale devices;Transistors;Ternary content-addressable memory (TCAM);nearest neighbor search;memory-augmented neural network (MANN);nanoelectromechanical (NEM) memory switch;CMOS-NEM hybrid circuit},
  doi={10.1109/LED.2021.3131184}}
@Article{types_optical_5,
author={Mao, Ruibin
and Wen, Bo
and Kazemi, Arman
and Zhao, Yahui
and Laguna, Ann Franchesca
and Lin, Rui
and Wong, Ngai
and Niemier, Michael
and Hu, X. Sharon
and Sheng, Xia
and Graves, Catherine E.
and Strachan, John Paul
and Li, Can},
title={Experimentally validated memristive memory augmented neural network with efficient hashing and similarity search},
journal={Nature Communications},
year={2022},
month={Oct},
day={21},
volume={13},
number={1},
pages={6284},
abstract={Lifelong on-device learning is a key challenge for machine intelligence, and this requires learning from few, often single, samples. Memory-augmented neural networks have been proposed to achieve the goal, but the memory module must be stored in off-chip memory, heavily limiting the practical use. In this work, we experimentally validated that all different structures in the memory-augmented neural network can be implemented in a fully integrated memristive crossbar platform with an accuracy that closely matches digital hardware. The successful demonstration is supported by implementing new functions in crossbars, including the crossbar-based content-addressable memory and locality sensitive hashing exploiting the intrinsic stochasticity of memristor devices. Simulations show that such an implementation can be efficiently scaled up for one-shot learning on more complex tasks. The successful demonstration paves the way for practical on-device lifelong learning and opens possibilities for novel attention-based algorithms that were not possible in conventional hardware.},
issn={2041-1723},
doi={10.1038/s41467-022-33629-7},
url={https://doi.org/10.1038/s41467-022-33629-7}
}




@ARTICLE{90s_associative_mem,
  author={Chisvin, L. and Duckworth, R.J.},
  journal={Computer}, 
  title={Content-addressable and associative memory: alternatives to the ubiquitous RAM}, 
  year={1989},
  volume={22},
  number={7},
  pages={51-64},
  keywords={Associative memory;Read-write memory;Content based retrieval;Information retrieval;Very large scale integration;Array signal processing;Algorithm design and analysis;Design optimization;CMOS process;High speed integrated circuits},
  doi={10.1109/2.30732}}

@ARTICLE{90s_associative_processing,
  author={Kida, L. S.},
  title={Associative Processing Implemented with Content-Addressable Memories}, 
  year={1991},
  keywords={Parallel processing (Electronic computers), Associative storage},
  doi={10.15760/etd.6060}}
@ARTICLE{image_processing1,
  author={Shin, Y.C. and Sridhar, R. and Demjanenko, V. and Palumbo, P.W. and Srihari, S.N.},
  journal={IEEE Journal of Solid-State Circuits}, 
  title={A special-purpose content addressable memory chip for real-time image processing}, 
  year={1992},
  volume={27},
  number={5},
  pages={737-744},
  keywords={Associative memory;Image processing;Computer aided manufacturing;CADCAM;Image analysis;Text analysis;Computer architecture;Labeling;Postal services;Clocks},
  doi={10.1109/4.133160}}
@ARTICLE{image_processing2,
  author={Panchanathan, S. and Goldberg, M.},
  journal={IEEE Transactions on Signal Processing}, 
  title={A content-addressable memory architecture for image coding using vector quantization}, 
  year={1991},
  volume={39},
  number={9},
  pages={2066-2078},
  keywords={Memory architecture;Image coding;Vector quantization;Computer architecture;Parallel processing;Distortion measurement;Computer aided manufacturing;CADCAM;Clustering algorithms;Iterative algorithms},
  doi={10.1109/78.134438}}




@ARTICLE{challenge1,
  author={Roth, Ron M.},
  journal={IEEE Transactions on Computers}, 
  title={Error-Detection Schemes for Analog Content-Addressable Memories}, 
  year={2024},
  volume={},
  number={},
  pages={1-14},
  keywords={Redundancy;Measurement;Vectors;Encoding;Hardware;Task analysis;Programming;Analog computation;Content-addressable memory;Error-detecting codes;Lee metric;Memristive devices},
  doi={10.1109/TC.2024.3386065}}
@inproceedings{challenge2,
author = {Pontarelli, S. and Ottavi, Marco and Salsano, A.},
year = {2010},
month = {11},
pages = {420 - 428},
title = {Error Detection and Correction in Content Addressable Memories by Using Bloom Filters},
volume = {62},
journal = {IEEE Transactions on Computers},
doi = {10.1109/DFT.2010.56}
}
@INPROCEEDINGS{challenge3,
  author={Varada, Anwesh and Agrawal, Sonali},
  booktitle={2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)}, 
  title={An Efficient SRAM-Based Ternary Content Addressable Memory (TCAM) with Soft Error Correction}, 
  year={2021},
  volume={},
  number={},
  pages={1-6},
  keywords={Application specific integrated circuits;Multiplexing;Associative memory;Random access memory;Error correction;Performance analysis;Delays;Ternary Content Addressable Memory (TCAM);multi-pumping;soft Error;2D parity;Application Specific Integrated Circuit (ASIC);Static Random-Access Memory (SRAM)},
  doi={10.1109/IEMENTech53263.2021.9614696}}


@article{memorywall_IMC,
  title={In-memory computing with resistive switching devices},
  author={Daniele Ielmini and H.-S. Philip Wong},
  journal={Nature Electronics},
  year={2018},
  volume={1},
  pages={333 - 343},
  url={https://api.semanticscholar.org/CorpusID:57248729}
}


@ARTICLE{soft_error,
  author={Baumann, R.C.},
  journal={IEEE Transactions on Device and Materials Reliability}, 
  title={Radiation-induced soft errors in advanced semiconductor technologies}, 
  year={2005},
  volume={5},
  number={3},
  pages={305-316},
  keywords={Error correction;Computer errors;Single event upset;Radiation effects;Space technology;Registers;Circuits;Control systems;Field programmable gate arrays;Paper technology;Radiation effects;reliability;single-event effects;soft errors},
  doi={10.1109/TDMR.2005.853449}}



@INPROCEEDINGS{app_networking1,
  author={Ooka, Atsushi and Atat, Shingo and Inoue, Kazunari and Murata, Masayuki},
  booktitle={2014 IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS)}, 
  title={Design of a high-speed content-centric-networking router using content addressable memory}, 
  year={2014},
  volume={},
  number={},
  pages={458-463},
  keywords={Computer aided manufacturing;Ice;Random access memory;Hardware;Conferences;Memory management;Tin},
  doi={10.1109/INFCOMW.2014.6849275}}


@INPROCEEDINGS{app_networking2,
  author={James-Roxby, P.B. and Downs, D.J.},
  booktitle={The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01)}, 
  title={An Efficient Content-Addressable Memory Implementation Using Dynamic Routing}, 
  year={2001},
  volume={},
  number={},
  pages={81-90},
  keywords={Routing;Associative memory;High-speed networks;Computer aided manufacturing;CADCAM;Telecommunication traffic;Encoding;Sorting;Runtime;Pattern matching},
  doi={}}




@ARTICLE{app_database1,
  author={Li, Huize and Jin, Hai and Zheng, Long and Liao, Xiaofei},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, 
  title={ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory}, 
  year={2020},
  volume={39},
  number={11},
  pages={4030-4041},
  keywords={Databases;Acceleration;Registers;Computer architecture;Graphics processing units;Field programmable gate arrays;Parallel processing;Content addressable memory (CAM);database query;nonvolatile memory;processing-in-memory (PIM)},
  doi={10.1109/TCAD.2020.3012860}}

@inproceedings{app_database2,
author = {Bandi, Nagender and Schnieder, Sam and Agrawal, Divyakant and Abbadi, Amr},
year = {2005},
month = {01},
pages = {},
title = {Hardware Acceleration of Database Operations Using Content-Addressable Memories.}
}


@article{types_quantum_1,
title = {TCAM/CAM-QCA: (Ternary) Content Addressable Memory using Quantum-dot Cellular Automata},
journal = {Microelectronics Journal},
volume = {46},
number = {7},
pages = {563-571},
year = {2015},
issn = {1879-2391},
doi = {https://doi.org/10.1016/j.mejo.2015.03.020},
url = {https://www.sciencedirect.com/science/article/pii/S0026269215000798},
author = {Luiz H.B. Sardinha and Douglas S. Silva and Marcos A.M. Vieira and Luiz F.M. Vieira and Omar P. {Vilela Neto}},
keywords = {Quantum-dot Cellular Automata, (Ternary) Content Addressable Memory, Nanocomputing, Memory},
abstract = {This paper describes a Content Addressable Memory (CAM) architecture and its ternary variant called Ternary Content Addressable Memory (TCAM) using the Quantum-dot Cellular Automata (QCA). QCA is an alternative to the current integrated circuit (CMOS) paradigm based on the characteristics of confinement and mutual repulsion between electrons. It is expected to run with clocks in high frequency (in THz order), in nanometers scale and with very low energy consumption. First, this work presents the basic building blocks (1-bit memory cell, array of memory cells, ternary memory line and encoder). Then, we describe the complete TCAM and CAM architectures. Finally, the proposed architectures are tested and validated using QCADesigner simulator, attesting their functionalities. If QCA consolidates as a possible CMOS substitute, this study can impact the design of future components that uses TCAM and CAM such as routers and switches respectively.}
}

@article{types_quantum_3,
title = {Content addressable memory cell in quantum-dot cellular automata},
journal = {Microelectronic Engineering},
volume = {163},
pages = {140-150},
year = {2016},
issn = {0167-9317},
doi = {https://doi.org/10.1016/j.mee.2016.06.009},
url = {https://www.sciencedirect.com/science/article/pii/S016793171630332X},
author = {Saeed Rasouli Heikalabad and Ahmad Habibizad Navin and Mehdi Hosseinzadeh},
keywords = {Quantum-dot cellular automata (QCA), Content addressable memory (CAM), Five-input minority gate, Nanoscale},
abstract = {Quantum-dot cellular automata (QCA) is an alternative to the CMOS circuits based on the characteristics of confinement and mutual repulsion between electrons. QCA can be used in designing ultra-dense, low-power, high speed and high-performance structures at nanoscales. Since memory is a very important part of each computer system, designing a high speed QCA memory is a significant issue. Content addressable memory (CAM) is a special type of memory structures which is used in a certain very fast searching applications. In this paper, a new five input minority gate-based CAM cell is introduced. QCADesigner has been used for simulation of the proposed structure and verifying its operation.}
}



@INPROCEEDINGS{app_2014,
  author={Veeramani, S and Kumar, Manas and Mahammad, S K Noor},
  booktitle={2013 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS)}, 
  title={Hybrid trie based partitioning of TCAM based openflow switches}, 
  year={2013},
  volume={},
  number={},
  pages={1-5},
  keywords={Indexes;IP networks;Partitioning algorithms;Random access memory;Complexity theory;Vegetation;Binary search trees},
  doi={10.1109/ANTS.2013.6802844}}


@INPROCEEDINGS{app_2015,
  author={Moradi, Mehrdad and Qian, Feng and Xu, Qiang and Mao, Z. Morley and Bethea, Darrell and Reiter, Michael K.},
  booktitle={2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)}, 
  title={Caesar: high-speed and memory-efficient forwarding engine for future internet architecture}, 
  year={2015},
  volume={},
  number={},
  pages={171-182},
  keywords={Internet;Routing;Memory management;Reliability;Information filters;Future Internet Architecture;Bloom Filters;Border Routers},
  doi={10.1109/ANCS.2015.7110130}}

@inproceedings{app_2016,
author = {Imani, Mohsen and Kim, Yeseong and Rahimi, Abbas and Rosing, Tajana},
booktitle={Conference: International Symposium on Low Power Electronics and Design (ISLPED), 2016}, 
year = {2016},
month = {08},
pages = {},
title = {ACAM: Approximate Computing Based on Adaptive Associative Memory with Online Learning},
doi = {10.1145/2934583.2934595}
}

@INPROCEEDINGS{app_2017,
  author={Imani, Mohsen and Peroni, Daniel and Kim, Yeseong and Rahimi, Abbas and Rosing, Tajana},
  booktitle={Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017}, 
  title={Efficient neural network acceleration on GPGPU using content addressable memory}, 
  year={2017},
  volume={},
  number={},
  pages={1026-1031},
  keywords={Associative memory;Biological neural networks;Artificial neural networks;Graphics processing units;Computer architecture;Acceleration},
  doi={10.23919/DATE.2017.7927141}
}

@INPROCEEDINGS{app_2018,
  author={Choi, Woong and Jeong, Kwanghyo and Choi, Kyungrak and Lee, Kyeongho and Park, Jongsun},
  booktitle={2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)}, 
  title={Content Addressable Memory Based Binarized Neural Network Accelerator Using Time-Domain Signal Processing}, 
  year={2018},
  volume={},
  number={},
  pages={1-6},
  keywords={Binarized neural network;Content addressable memory;Time-domain signal processing},
  doi={10.1109/DAC.2018.8465903}}



@article{app_2020,
author = {Graves, Catherine and Li, Can and Sheng, Xia and Miller, Darrin and Ignowski, Jim and Kiyama, Lennie and Strachan, John Paul},
year = {2020},
month = {08},
pages = {2003437},
title = {In‐Memory Computing with Memristor Content Addressable Memories for Pattern Matching},
volume = {32},
journal = {Advanced Materials},
doi = {10.1002/adma.202003437}
}

@misc{app_2024,
      title={Deep Random Forest with Ferroelectric Analog Content Addressable Memory}, 
      author={Xunzhao Yin and Franz Müller and Ann Franchesca Laguna and Chao Li and Wenwen Ye and Qingrong Huang and Qinming Zhang and Zhiguo Shi and Maximilian Lederer and Nellie Laleni and Shan Deng and Zijian Zhao and Michael Niemier and Xiaobo Sharon Hu and Cheng Zhuo and Thomas Kämpfe and Kai Ni},
      year={2021},
      eprint={2110.02495},
      archivePrefix={arXiv},
      primaryClass={cs.ET},
      url={https://arxiv.org/abs/2110.02495}, 
}





@INPROCEEDINGS{app_2021_SAT,
  author={Park, Soowang and Nam, Jae-Won and Gupta, Sandeep K.},
  booktitle={2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)}, 
  title={HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks}, 
  year={2021},
  volume={},
  number={},
  pages={29-34},
  keywords={Design automation;Integrated circuit interconnections;Benchmark testing;Hardware;Software;Acceleration;Artificial intelligence;Custom hardware;SAT;BCP;von Neumann machine;CAM},
  doi={}}